Introduction
As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market.

Your Role and Responsibilities
IBM Research at Albany, NY is seeking a process integration engineer who will push boundaries in the integration of advanced logic and next generation semiconductor packaging technologies. In this role, you will be responsible for leading the integration of processes that span the back end of the line (BEOL) silicon semiconductor processing, wafer finishing, and grindside processing. You will have a critical role in driving the development of 2.x and 3D silicon technologies and beyond. The position requires close collaboration with cross-functional and multi-company working teams that include engineers engaged in unit process development, materials and process development, structural/chemical/electrical analysis, and layout design.

• 5+ years hands on experience in one or more of these areas: thru silicon via (TSV) process integration, hybrid bonding, temporary bonding-debonding, bumping, wafer level fan out, semiconductor packaging technology.
• 5+ years hands on experience in the back end of the line (BEOL) process integration covering Copper interconnects and dual damascene integration flow.
• 5+ years experience with interpreting failure analysis from structural and chemical characterization techniques.
• 5+ years experience or knowledge in performing quantitative analysis of electrical data to interpret experimental results.
• 5+ years experience with design of experiments, process controls, and statistical data analysis.
• 5+ years experience or knowledge in semiconductor and Chip Package Interaction (CPI) reliability analysis and failure mechanisms.
• Bachelor's degree in a science or engineering discipline.

• 10+ years hands on experience in one or more of these areas: thru silicon via (TSV) process integration, hybrid bonding, temporary bonding-debonding, bumping, wafer level fan out, semiconductor packaging technology.
• 10+ years experience with interpreting failure analysis from structural and chemical characterization techniques.
• 10+ years experience or knowledge in performing quantitative analysis of electrical data to interpret experimental results.
• 10+ years experience with design of experiments, process controls, and statistical data analysis.
• 10+ years hands on experience in the back end of the line (BEOL) process integration covering Copper interconnects and dual damascene integration flow.
• 10+ years experience or knowledge in semiconductor and Chip Package Interaction (CPI) reliability analysis and failure mechanisms.
• MS/PhD degree in a science or engineering discipline.