ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Meta is hiring ASIC Verification Engineer with background in Simulation Acceleration using Emulation and Hybrid Platforms within the Infrastructure organization. We are looking for individuals with experience in Simulation Acceleration and Emulation to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

• Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology to be used across the group, both at the Cluster and at the SoC level
• Work with Architecture and Design teams to come up with functional, use case and performance test plan for the DUT
• Define Verification scope, create environment, testplans and close use case scenarios and performance using targeted tests at Cluster and SoC level
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Develop and drive continuous Hybrid Verification improvements using the latest methodologies, tools and technologies from the industry
• Build reusable/scalable environments for Hybrid Verification. Evaluate and recommend solutions for Hybrid Verification and Simulation Acceleration
• Provide training for internal teams and mentoring engineers related to Hybrid Verification Methodology

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• At least 9+ years of relevant experience
• Track record of 'first-pass success' in ASIC development
• Hands-on experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification
• Experience of working with Zebu, Palladium, Veloce HW platforms
• Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies
• Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments
• Experience in architecting and implementing Hybrid Verification infrastructure and executing verification cycle
• Experience using analytical skills to craft novel solutions to tackle industry-level complex designs
• Demonstrated experience with effective collaboration with cross functional teams

• Experience in development of Simulation Acceleration and Hybrid verification environments from scratch
• Experience in performance verification of complex compute blocks like CPU, GPU or HW Accelerators, Ethernet, PCIe, DDR, HBM etc
• Experience in verification of Data-center applications like Video, AI/ML and Networking designs or integration verification of high-speed interfaces like Ethernet PCIe, DDR, HBM
• Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification
• Experience with verification of ARM/RISC-V based sub-systems or SoCs
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with simulators and waveform debugging tools
• Experience working across and building relationships with cross-functional design, model and emulation teams