ASIC DV Engineer, PCIe Verification

Meta is hiring ASIC Verification Engineer with in-depth understanding of PCIe Express within the Infrastructure organization. We are looking for individuals with experience in verification of PCIe Switch, Root Complex and Endpoint to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

• Develop and execute verification plans, test cases, and scripts to ensure PCIe interface functionality, performance, and compliance with industry standards.
• Collaborate with design teams to understand the PCIe interface architecture and identify potential issues.
• Create and maintain testbenches, including simulation models and tests
• Perform simulation-based testing, including functional, performance, and compliance testing
• Analyze test results, identify defects, and work with design teams to resolve issues.
• Stay up-to-date with industry trends, standards, and best practices related to PCIe verification
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Mentor engineers to drive and deliver high confidence verification for highly complex ASIC projects.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• At least 15+ years of relevant experience
• Track record of 'first-pass success' in ASIC development
• Good knowledge of PCIe specifications, protocols, and standards covering Root Complex, End Point and Switch
• Good hands-on verification experience in PCIe Transaction, Link and Physical layer.
• Hands-on experience in Verilog, SystemVerilog, UVM , C/C++, Python based verification
• Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup
• Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments
• Experience in architecting and implementing DV setup for complex Subsystem and ASICs.
• Experience using analytical skills to craft novel solutions to tackle industry-level complex designs
• Demonstrated experience with effective collaboration with cross functional teams

• Experience in development of PCIe Gen6/Gen7 DV testbench and infrastructure from scratch
• Hands-on experience with integration and usage of varied PCIe vendor VIP
• Experience in performance verification of PCIe Sub-System for AI/ML Applications etc
• Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with simulators and waveform debugging tools
• Experience working across and building relationships with cross-functional design, model and emulation teams