Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• 1 year of experience with verification methodology such as UVM.
  
• 1 year of experience in the verification of SoCs.
  
• Experience with SystemVerilog, SVA and functional coverage.
  

Preferred qualifications:

• Master's degree in Electrical Engineering.
  
• Experience creating and using verification components and environments in standard verification methodology.
  
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Verification planning and test execution with emphasis on meeting stringent AI/ML performance. Work with robust, constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of AI/ML workloads on TPU hardware. You will collaborate closely with design and verification engineers in active projects and perform verification.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  
• Identify and write all types of coverage measures for stimulus and corner-cases.
  
• Debug tests with design engineers to deliver functionally correct design blocks.
  
• Manage coverage measures to identify verification holes and show progress towards tape-out.