Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or in a related technical field, or equivalent practical experience.
- 3 years of experience designing Register-Transfer Level (RTL) digital logic using SystemVerilog for FPGA/ASICs or equivalent practical experience.
- 3 years of experience in Application-Specific Integrated Circuit (ASIC) digital design, including SystemVerilog, scripting languages and synthesis.
- Master's Degree or PhD in Electrical Engineering, Computer Science, or in a related technical field.
- Understanding of computer architecture including industry standard interfaces and memory subsystems.
- Knowledge of accelerators like Machine Learning (ML), or Graphics Processing Units (GPU) or similar high performance designs.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Engage with Architects to align the feature specifications.
- Engage with Verification and Silicon Validation teams to ensure functionality of the design.
- Provide input on synthesis, timing closure, and Physical Design of digital blocks.
- Perform power, area and performance trade-offs for digital designs and architectures.
- Apply engineering best practices (e.g. code review, testing, refactoring) to the design and implementation of ASIC blocks.