At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Validation Engineer 芯片验证测试（测试方向）
Job Description:
负责Highspeed Serdes 和 DDR IP 测试评估版的原理图和PCB 设计；
负责PCIE, USB, 10G-KR Serdes IP 一致性测试；
负责DDR4/LPDDR4X/DDR5/LPDDR5 IP 一致性测试。
依据实际的测试方案，编写自动化测试脚本
协同设计者解决IP验证测试遇到的问题
Requirements:
微电子, 电子工程或计算机相关专业，全日制本科硕士
扎实的数字和模拟电路基础知识
有一定的硬件设计基础，熟练使用示波器，BERT 及逻辑分析仪
熟悉Python/C等脚本语言
较强的中英文沟通写作能力, 较强的问题分析以及团队合作能力
有芯片设计或测试相关工作经验优先
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Client-provided location(s): Nanjing, Jiangsu, China
Job ID: Cadence-R48860
Employment Type: Full Time
Perks and Benefits
Health and Wellness
- Dental Insurance
- Vision Insurance
- Life Insurance
- Short-Term Disability
- Long-Term Disability
- FSA
- HSA With Employer Contribution
- Fitness Subsidies
- On-Site Gym
- Mental Health Benefits
- Virtual Fitness Classes
- Health Insurance
Parental Benefits
- Birth Parent or Maternity Leave
- Non-Birth Parent or Paternity Leave
- Fertility Benefits
- Adoption Assistance Program
- Family Support Resources
- Adoption Leave
Work Flexibility
- Flexible Work Hours
- Hybrid Work Opportunities
Office Life and Perks
- Casual Dress
- On-Site Cafeteria
- Holiday Events
Vacation and Time Off
- Paid Vacation
- Unlimited Paid Time Off
- Paid Holidays
- Personal/Sick Days
- Leave of Absence
- Volunteer Time Off
Financial and Retirement
- 401(K) With Company Matching
- Stock Purchase Program
- Performance Bonus
- Financial Counseling
Professional Development
- Tuition Reimbursement
- Promote From Within
- Mentor Program
- Access to Online Courses
- Internship Program
- Leadership Training Program
