At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry. This position is for a synthesis and design engineer.

Responsibilities

• Develop/improve highly automated and customizable synthesis design flows for a highly configurable design using modern methodologies.
• Develop and recommend better design method practices to enable better synthesis convergence.
• RTL/logic design skills as well as physical design skills for timing closure.
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution.
• Run, debug, and fix signoff closure issues in static timing analysis (STA).
• Full chip & block level timing constraints ensuring area & timing optimization.
• Participate in an engineering team to advance our product.

• BS in Electrical, Computer Engineering or equivalent experience with 7+ years of ASIC and/or physical design flow experience; MS preferred.
• Familiar with Verilog and ASIC design along with experience in commercial EDA tools (Lint, Physical Synthesis, CDC, LEC, Formal).
• Have a strong proficiency in at least one of Python, Perl , Tcl, C/C++
• Experience with logic synthesis, physical design, formal equivalence checking.
• Scripting experience with Python, Tcl, or Perl
• Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment.
• Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods.