At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Are you ready to join the team that is changing the way the world does chip design? Today's chips and systems are becoming too complex to continue design with the traditional RTL design techniques so the industry is moving to a higher level of design abstraction using SystemC and High Level Synthesis.

The Stratus High Level Synthesis (HLS) product from Cadence synthesizes SystemC input models into high quality Verilog RTL based on a target technology library and user constraints. Stratus is already in production flows at many of the industry's top semiconductor and systems companies.

In this role, you will be responsible for the design, implementation and maintenance of one of the many complex phases of the Stratus synthesis process. This includes implementing in C++ many modern algorithms, design and implementation of complex data structures and understanding the hardware implications of C++ synthesis.

• Own, develop and maintain a portion of the Stratus C++ code base
• Absorb requirements specifications for new features and write accompanying function specifications for the development process
• Work closely with team members to develop techniques to increase the capability, capacity and stability of Stratus
• Interface with regression system to test code commits as part of the development process

• BS in CS or EE (or equivalent science) or 1 year of equivalent experience
• MS in CS or EE (or equivalent science)

• Good working knowledge of Modern C++ software design
• Strong understanding of software data structures and algorithms
• Basic understanding of the Verilog RTL design process
• Hardware, especially VLSI, design a plus
• Scripting language skills in Perl, Python or TCL a plus
• Excellent written and oral communication skills
• Team player. Responds to input from others and willing to speak up when help or information is needed