At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a dynamic and growing team of engineers developing high-speed physical IP for industry-standard protocols. The successful candidate will be a highly self-motivated and results-oriented member of a small team of engineers that can learn and improve existing digital flows. The candidate will primarily be responsible for front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with the digital, analog and application teams. Candidate should be willing to work full time in the San Jose office.

• Digital microarchitecture definition and documentation
• RTL logic design, debug and functional verification
• IP integration and verification
• Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.
• Understanding of digital architecture trade-offs for power, performance, and area
• Understanding of proper handling of multiple asynchronous clock domains and their crossings
• Understanding of Lint checks and proper resolution of errors
• Understanding synthesis timing constraints, static timing analysis and constraint development
• Understanding of fundamental physical design flows and stages
• Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow.
• Exhibit excellent communication skills and be self-motivated and well organized.
• Experience with FPGA and/or emulation platform is a plus.
• Firmware development of embedded microcontroller systems is a plus.