KEY RESPONSIBILITIES / PREFERRED EXPERIENCE:

The focus of this role is to plan, build, and execute the verification of new and existing features for SOCs, resulting in no bugs in the final design to tape-out.

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements
• Build testbench components to support the next generation IP
• Maintain or improve current test libraries to support IP level testing
• Create hardware emulation build to verify the IP functional performance
• Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility
• UPF based RTL low power verification
• Proficient in IP level ASIC verification
• The candidate must have prior experience in testplan creation, developing a testbench from cratch, RTL simulation, coverage driven verification and Gate-level simulation (GLS).
• Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor/SOC design.
• Proficient in debugging firmware and RTL code using simulation tools
• • Proficient in using UVM testbenches and working in Linux and Windows environments
• • Experienced with Verilog, System Verilog, C, and C++
• • CPU/Graphics pipeline knowledge
• • Automating workflows in a distributed compute environment.
• • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• • Good working knowledge of SystemC and TLM with some related experience.
• • Scripting language experience: Perl, Ruby, Makefile, shell preferred.