We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
Meet the Team
As part of central CAD group, CAD Physical Verification (PV) team is responsible for developing and supporting various PV decks like DRC, antenna, dummy fill, LVS and extraction. Collaborates and collects specs from other teams to code decks like PERC, float, density, xor from scratch. The team is also responsible for developing and automating various flows and methodologies to improve verification quality and optimize performance.
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Responsibilities
- Development of various physical verification rule decks like DRC, dummy fill, Antenna and other custom decks
- Conduct and drive impact analysis meetings with stakeholders for deck updates
- Collaborate closely with CAD, ESD, design, layout and foundry teams to obtain requirements for deck development.
- Support design and layout teams to resolve any PV related issues during design development cycle
- Conduct code reviews and create custom QA testcases to validate the quality of rule decks.
- Develop and maintain PV flows and methodologies to improve quality and performance
- Perform new tool/feature evaluations and benchmarks.
- Work closely with external vendors to report and track bugs in the software
Skills you'll need:
- 5+ years of related professional experience
- Bachelor's or Master's degree in electrical engineering
- Proficiency in developing and supporting DRC rule decks in Calibre SVRF or similar languages
- Experience in coding LVS, extraction and PERC rule decks is a plus
- Experience working with design/layout engineers in debugging PV issues.
- Knowledge of using physical verification tools like Calibre RVE, Calibre DRV, Virtuoso layout editor etc
- Proficiency in scripting languages like PERL/Python/Shell for developing custom scripts
- Experience in collaborating with different teams for collecting initial specs, deck development and support and leading deck impact analysis meetings.
- Ability to work independently, drive decision-making, detail oriented and documentation skills are critical.
Benefits & Perks
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
- Equity Rewards (RSUs)
- Employee Stock Purchase Plan (ESPP)
- Insurance plans with Outpatient cover
- National Pension Scheme (NPS)
- Flexible work policy
- Childcare support
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.