As a member of our team, you will be shaping the future of cybersecurity. We work fast, value ongoing learning, and we respect each employee as a unique individual. Knowing we all have different needs, our development and personal wellbeing programs are designed to give you choice in how you are supported. This includes our FLEXBenefits wellbeing spending account with over 1,000 eligible items selected by employees, our mental and financial health resources, and our personalized learning opportunities - just to name a few!

At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full time from our office with flexibility offered where needed. This setup fosters casual conversations, problem-solving, and trusted relationships. Our goal is to create an environment where we all win with precision.

Your Career

As an ASIC Integration and Physical Design Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for performance, reliability, and power efficiency. You will integrate third-party IPs and PANW designs at the subsystem and top levels. You will guide the design team on strategies for clocks, resets, and synchronization. You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints, and optimizing power consumption.

Your Impact

• Integrate PANW designs at the subsystem and top levels, ensuring robust solutions for clocks, resets, feedthroughs, and DFT
• Integrate RAMs, CAMs, custom IPs, and IO pads throughout the design hierarchy
• Collaborate with external ASIC vendors to define optimal floorplans, power grids, clocking strategies, and custom routing
• Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption, and validating constraints

Your Experience

• BS in EE, CE, or CS required. MSEE preferred
• Minimum 5 years experience in ASIC integration and physical design
• Demonstrated success in taking ASICs to mass production
• Expertise in synthesis and static timing analysis

Required strengths

• Integrating RTL modules, memories, custom IPs, and IOs at multiple hierarchical levels
• Implementing integration RTL in SystemVerilog
• Defining and validating timing constraints and exceptions
• Closing timing with static timing analysis and verifying clock domain crossing paths
• Advising designers on optimizing congestion and power dissipation

Preferred experience

• Creating automated flows for top-level integration
• Physical synthesis with Fusion Compiler
• RTL quality checks - Lint, CDC, RDC, X-verification
• Physical design for networking ASICs with wide data paths and memory-dominant floorplans
• Skilled in writing powerful, modular, and scalable programs in Python / Perl / Unix shell to automate integration and physical design
• Demonstrated ownership and independence in planning, managing multiple priorities, driving vendors, and reporting status
• Strong leadership, collaboration, and communication skills

The Team

We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices.

Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers' existing investment in data, sensors, and enforcement points.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $120000 - $193500/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here.

Our Commitment

We're problem solvers that take risks and challenge cybersecurity's status quo. It's simple: we can't accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.