With the slowdown in Moore's law, silicon power management and hardware power optimizations become a critical part of the development of silicon ASICs. We are positioning you for a key role to take on this challenge and become part of our team, so we can continue developing the best devices in the industry!

NVIDIA's network horizontal power group is seeking for a highly-skilled, physical design engineer to explore, define and assimilate methods for optimizing our products' power with respect to performance and cost. In your role you'll be responsible to develop methodologies, improve tools and flows, driving power optimization and examine silicon power & performance. We are searching for a hard-working, highly motivated, engineer which has both excellent technical skills as well as outstanding personal skills.

• lead power execution in prime power and a power model for various networking product lines.
• Establish estimation and optimization techniques for rtl design and physical design teams.
• Improve estimation quality and pre2post correlation
• Develop methodologies and flows across the organization for both pre and post-silicon analysis.
• Improve RTL to gate level power aware flows and automation.

• B.Sc. degree or equivalent experience in Electrical Engineering.
• 2+ years of significant shown experience.
• Strong physical design fundamentals, knowledgeable in timing analysis, power analysis, and scripting.
• Excellent problem-solving, partnership, and interpersonal skills.