We are looking for a Senior Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence.

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.
• Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.
• IP layout will comprise of significant digital components.
• Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts
• Follow company procedures and practices for IC layout activities.

• B.E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process.
• Detailed knowledge of industry standard EDA tools for Cadence.
• Experience with layout of high-performance memories of various types.
• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)
• Experience with floor planning, block level routing and macro level assembly.
• Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.