NVIDIA's Networking ASICs are the world leaders in performance and efficiency, and we are continually innovating in creative and unique ways to improve our ability to deliver extraordinary solutions in a wide range of sectors. We are looking for an experienced ASIC Packaging Engineer, focusing on Mechanical/Thermal modeling of ASIC packages.

Package engineer will join IC package development team in Yokneam, leading advanced IC packaging projects at the cutting edge of technology. In this position you will collaborate with the best technical and design teams, plan schedules, resolve costs and lead packaging, manufacturing, and electrical design issues. You will be working with world's leading manufacturers.

What you'll be doing:

• Working with cross functional teams to define advanced package thermal/ mechanical specifications for advanced packages 2.5D, 3D, wafer level packaging.
• Perform advanced package modeling for advanced custom silicon comprising single-chip/multi-chip and 3D and wafer packaging to ensure our ASICs meet/exceed performance and reliability targets.
• Model and simulate package manufacturing and assembly process for advance packaging process chip on wafer on substrate (S/L/R), silicon interposer, chiplet attach and SMT process.
• Perform advanced package stress analysis and "what-if" scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package manufacturability and reliability for next generation versions of current products.
• Packaging materials (e.g. underfill, mold compound, solder ball metallurgy, TIM, substrate, and lid attach adhesive) characterization to support new packaging architecture and develop material models to precisely describe package physical behavior.
• Responsible for designing robust and reliable mechanical package architecture.

• Bachelor's degree in mechanical engineering, Electrical Engineering, or equivalent experience.
• 10+ years of experience in FEA modeling semiconductor related fields.
• Experience with complicated numerical simulation results against first principles such as strength of materials solutions.
• Consider as an expert with hands-on experience of major FEM tools with skill to calibrate modeling and results with existing empirical data.
• Hands-on mechanical modeling stress analysis experience for interposer or fanout package design for both organic and inorganic interposer with or without bridges such as Cowos-L, cowos-R, EMIB, 3D IC structural concept and for lidded or lidless package
• Curious and creative problem solver, well organized and multi-tasker.
• Team oriented, able to move and motivate peers, strong inter- personal and interpersonal skills (verbal and written).
• High self-learning and self-motivation skills.
• Leadership skills, capability to lead cross company projects that involve cross functional teams in Israel & abroad.

• Master's or PhD degree in Materials engineering.
• In-depth knowledge of modeling of flip chip, 2.5D and 3D and wafer packaging technologies package design.
• Programming experience using Matlab, Python and fundamental machine learning capability is plus.
• Background in semiconductor manufacturing processes.
• Excellent social skills.