NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD intern at NVIDIA, you'll learn and work on the tasks from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work.

• Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
• Synthesis, RTL/netlist quality check, formal verification, function eco creation
• Constraints creation and validation, timing budget, work with ASIC team to analyze/resolve function timing issues, achieve all special timing closure, such as io, test, clock, async etc.
• Work in conjunction with PR engineers for chip implementation to achieve full chip timing closue
• Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas
• Methodology in any of above areas.

• Currently pursuing a Master's or PhD degree within a relevant or related field
• Strong knowledge in IC design
• Passionate about technology research and IC backend
• Self-driven, good leaning ability, good teamwork
• Excellent communication skill, proficient in English reading and writing

• Experience in IC backend implementation
• Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC)
• Proficient user of Python or TCL