NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

• Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system.
• Work closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.
• Understand key performance use cases or the product. Develop workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on our products.
• You will be responsible to make architectural trade-offs based on feature/performance/power requirements, analyse system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.
• Developing test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's.
• Creating verification environment using UVM methodology and reusable bus functional models, monitors, checkers and scoreboards.
• Driving functional coverage driven verification closure.
• Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
• Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
• Chip level Integration, physically partitioning and floor planning along with Physical Verification and EM IR Drop
• You will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
• In addition, you will help develop and deploy DFT methodologies for our next generation products.
• Be apart of innovation to strive improve the quality of DFT methods.
• Work with architects, designers and post-silicon teams.

• BTech/MTech with 2+ years of experience in micro-architecture, RTL development of complex designs.
• Possess strong digital design fundamentals.
• Preferably have a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring up and lab debug is a prerequisite for this role.
• If you have experience in at least a few of the following skills, we will have an excellent match for our needs:

• GPU / CPU / SOC Performance verification and analysis.
• CPU, Memory controller, Bus Interconnect, Cache coherency
• IP / SOC Design, Micro-architecture across High Speed IO controller (UFS/PCIE/ XUSB), Network on Chip / 10G Ethernet MAC and (or) Switch
• IP / SOC
• Graphics Processing Unit (GPU Design & Verification)
• BOOT and Power management features for complex SOC's
• FPGA Prototype with prior experience in HAP
• Good debugging and analytical skills.
• Good interpersonal skills and ability to work as an excellent teammate
• Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization