Primary Functions:
Solid State Technicians perform a variety of processes to support the development, fabrication, testing, and assembly of semiconductor devices in accordance with operational goals. Solid State Technicians are responsible for the setup, operation, and adjustment of a variety of process and measurement tools to support integrated circuit production and engineering development efforts. Solid State Technicians may be asked to perform process calculations, summarize data, prepare basic reports, and maintain electronic data logs for engineering staff. Solid State Technicians must adhere to all safety policies and maintain a clean, orderly work area at all times. Given the diverse nature of the production needs at ATL, a Solid State Technician will be assigned to one or more of the following specific process areas:
Wafer Fabrication

Chemical Mechanical Planarization (CMP): Using a combination of chemical reactivity and mechanical forces to remove excess material from the surface of a wafer with high precision and uniformity.

* Chemical Vapor Deposition (CVD): Creating high quality, high performance thin films where a volatile precursor gas reacts with the wafer/substrate surface in a chamber.

* Diffusion: Using high temperature furnaces to drive species into the substrate or to create thin inter facial layers by introducing a gas or solid source material to modify electrical properties.

* Dry Etch: Removing material deposited onto wafers by using reactive ion etching (RIE) for anisotropic removal or through inductively coupled plasma (ICP) etch for isotropic removal of material.

* Implant: Changing physical, chemical, or electrical properties of a substrate by accelerating and bombarding ions of a particular element into the wafer at a high energy.

* Metal Deposition: Metallic films can be deposited onto substrates using a variety of techniques including sputter physical vapor deposition (PVD), electron beam PVD, thermal evaporation, and electroplating.

* Photolithography: Patterning onto the surface of a wafer by exposing a specific wavelength of light through a photo mask onto a photosensitive material spun onto the wafer surface.

* Clean / Wet Etch: Cleaning substrates before a sensitive downstream process step or stripping undesirable films from surfaces through isotropic wet etch processes.

* Pre-Assembly: Wafer bonding, lapping, polishing, grinding, taping, and sawing processes that are performed in advance of moving wafers to the assembly area.

* Metrology / Inspection: Monitoring of critical product specifications including critical dimensions, overlay, film thickness, particle adders, sheet resistance, or other optical defects.

Electrical Test

DC / Parametric Testing: Recording electrical parameters of unit cells and subsets of active circuitry to evaluate and monitor the performance of various technologies as an early screening test for final test and yield prediction.

* Application Specific Integrated Circuit (ASIC) Test: Functional electrical test using a wide variety of test systems, wafer probers, and test hardware to quantify electrical performance of analog, digital, and memory circuits on product wafers and packaged parts.

* Radio Frequency Monolithic Microwave Integrated Circuit (RF MMIC) Test: Functional electrical test using various probers and test instrumentation to measure electrical RF parameters such as microwave mixing, power amplification, and switching on whole wafers and discrete semiconductor devices.

Assembly

Wafer Saw: Dicing a wafer into individual, discrete semiconductor devices after being attached to a wafer frame and sent to tooling that cuts the mounted wafer into per-determined die size.

* Die Sort: Picking pre selected discrete semiconductor devices from a diced wafer identified at wafer test are placed into chip carriers.

* Die Mount: Attaching one or more discrete semiconductor devices onto the die cavity of a package that protects from damage and corrosion, supports heat dissipation, and facilitates electrical connection to the outside world.

* Wire Bond: Creating an electrical connection to the external environment by attaching very fine wires between pads on a semiconductor device and the pads of a semiconductor package.

* Lidding / Marking: Packaging a semiconductor device and creating a hermetic seal capable of meeting specific leak rates. The package then receives identification/traceability marks using either ink marking or laser marking processes.

This is an SEA Union Represented position.
This is a 1st shift position.
Basic Qualifications:

High school graduate or equivalent. Must possess an Associate Degree (minimum of 60 semester hours) or two years (minimum 60 semester hours) of college level study. Must possess a minimum of 6 semester hours in Science, Technology, Engineering, Mathematics, or a related field of study.

* Candidates may substitute two years of experience working with electronic circuits for every 30 semester hours of college level study.

Preferred Qualifications:

Ability to obtain and maintain a DoD Secret Level Clearance

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.