Are you interested in exploring a career on the cutting edge of IC circuit design? You'll leverage your current experience and join our team of scientists and engineers in design of integrated circuits for emerging applications in low temperature environments. You'll work in a fast-paced team environment alongside a broad array of scientists and engineers to make these design solutions a reality.
The Microelectronics Designs and Applications (MDA) business area of Northrop Grumman Mission Systems (NGMS) is seeking motivated and experienced Integrated Circuit (IC) Layout Engineers to join our team in the design and layout of custom, low-power, analog and mixed signal circuits. The ideal candidate will have experience designing in a range of technology nodes including advanced nodes as well as more conventional planar technologies. Experience with layout and modeling of transmission lines and inductors is desirable. Candidate will work with IC designers to produce layouts that comply with best design practices. This position requires work on site in either Sacramento, CA or Baltimore, MD area facilities.
What You'll get to Do:
Tasks will include circuit layout, physical verification (LVS, DRC), and parasitic extraction for a variety of analog/mixed signal circuits, Process Control Monitor (PCM) circuits, and physical measurement structures. Additional responsibilities involve floor planning, supporting design engineers, and coordination with mask team in reticle composition and mask order tapeout activities. The right candidate will be comfortable in a dynamic environment with rapidly developing technologies and tools. The candidate must be able to work independently to take a schematic design through layout and physical verification and create a test plan based on circuit requirements. Strong communication skills are required.
This position can be filled at the Principal IC Layout Engineer OR the Sr. Principal IC Layout Engineer.
Basic Qualifications for Principal IC Layout Engineer:

Bachelor's degree plus 5 years of relevant experience; Will consider 9 years of applied experience in lieu of degree requirement. (3 years with technical MS or 0 years with a PhD)

* Demonstrated experience with hands-on custom circuit design.

* Experience with modern IC design tools (Cadence Virtuoso) for schematic capture and custom layout; physical verification using Assura or Calibre.

* Ability to navigate file structures in the LINUX environment.

* Demonstrated ability to meet tight deadlines and milestones according to program schedule.

* Demonstrated experience in problem solving and analytical skills.

* Excellent communication skills, able to efficiently disseminate information to leadership and respective working group.

* Able to obtain and maintain a TS/SCI with polygraph security clearance per business requirements.

* US Citizenship is a required

Basic Qualifications for Sr. Principal IC Layout Engineer:

Bachelor of Science degree in Electrical Engineering or related field with 9 years of experience in either Analog, Digital or Mixed Signal Circuit design. Will consider 13 years of applied experience in lieu of degree requirement. (7 years with technical MS or 4 years with a PhD).

* Experience with modern IC design tools (Cadence Virtuoso) for schematic capture and custom layout; physical verification using Assura or Calibre.

* Ability to navigate file structures in the LINUX environment.

* Understanding of semiconductor manufacturing and testing processes.

* Demonstrated ability to meet tight deadlines and milestones according to program schedule.

* Demonstrated experience in problem solving and analytical skills.

* Excellent communication skills, able to efficiently disseminate information to leadership and respective working group.

* Able to obtain and maintain a TS/SCI with polygraph security clearance per business requirements.

* US Citizenship is a required

Preferred Qualifications for Principal IC Layout Engineer/Sr. Principal IC Layout Engineer:

Experience with hierarchical design, top-level floor-planning, and chip-level integration.

* Understanding of the Process Design Kit (PDK) structure (including tech files, verification rule files, Pcells etc.)

* 10+ years of experience in the layout and verification of analog and/or mixed signal circuits in planar and/or advanced CMOS nodes.

* Knowledge of advanced Cadence Virtuoso capabilities for improving task efficiency.

* Experience with laying out and characterizing digital standard cells.

* Experience with commercial tools for modeling of high frequency structures (e.g. transmission lines).

* Experience using scripting languages SKILL or Python.

* Experience with product validation and testing.

* Experience creating and maintain chip design schedules and meeting tight deadlines in critical path of overall program schedule.

* Ability to and create a test plan based on circuit requirements.

* Active TS/SCI Security Clearance.

#NGMCENG
What We Can Offer You:
Northrop Grumman provides a comprehensive benefits package and a work environment which encourages your growth and supports the mutual success of our people and our company. Northrop Grumman benefits give you the flexibility and control to choose the benefits that make the most sense for you and your family.
Your benefits will include the following: Health Plan, Savings Plan, Paid Time Off and Additional Benefits including Education Assistance, Training and Development, 9/80 Work Schedule (where available), and much more!
Salary Range: $102,400 - $153,600
Salary Range 2: $127,000 - $190,600
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.