The Networked Information Solutions (NIS) Advanced Processing Solutions (APS) business is seeking a Principal or Senior Principal Circuit Design Engineer / Layout Engineer. The ideal candidate will have solid understanding of microelectronic electrical principles, demonstrated organizational skills and a willingness to learn and grow in a team environment. The development nature of our foundry activities will provide a willing candidate the opportunity to grow into an integral member of the Northrop Grumman design community.
Responsibilities (including, but not limited to):

Create custom designs and layouts that could include Process Control Monitor (PCM) structures, reticle alignment marks, and physical measurement structures. Mentoring and guidance are provided by process engineers, photo lithography engineers and peer engineers.

* Provide floor planning guidance and support.

* Create chip designs in various technologies for process prove-in, experimentation, and test support.

* Perform both frontend and backend verification of designs.

* Participate in reticle composition and tape out activities.

* Document work performed.

Additional Valuable Skills:

Experience using Cadence design suite of tools to perform full and semi-custom design work.

* Knowledge of Cadence Virtuoso L/XL/EXL capabilities that enhance design task efficiency.

* Knowledge of semiconductor device physics and analog/mixed signal integrated circuit design.

* Experience laying out or characterizing digital standard cells or memory elements.

* Design simulation using industry tools such as ANSYS/HFSS or ADS.

* Building scripts, in an agreed upon programing language, to automate repetitive tasks or facilitate an increase in productive work.

* Create and document flows for future re-use and quality control.

* Knowledge of an industry programing language: Shell, Python, Perl, TCL/TK or equivalent.

* Experience with any of the following:

Behavior modeling skills using Verilog-A or Verilog-AMS.

* Full-chip functional/performance verification methods.

Experience collaborating with research staff/quantum physicists to realize proof of principle designs.

This position requires onsite support at our Linthicum, MD, Annapolis Junction, MD or McClellan, CA campuses.
This position can be filled as a Principal Circuit Design Engineer / Layout Design Engineer OR a Senior Principal Circuit Design Engineer / Layout Design Engineer.

Basic Qualifications for a Principal Circuit Design Engineer / Layout Design Engineer:

Bachelor's Degree in a STEM related field with 5 years of related experience; 3 years with Masters; 0 years with PhD. An additional 4 year's experience in lieu of degree will be considered.

* Excellent verbal, written, and interpersonal communication skills.

* Navigate file structures in the LINUX environment.

* US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.

Basic Qualifications for a Senior Principal Circuit Design Engineer / Layout Design Engineer:

Bachelor's Degree in a STEM related field with 8 years of related experience; 6 years with Masters; 4 with a PhD. An additional 4 year's experience in lieu of degree will be considered.

* Excellent verbal, written, and interpersonal communication skills.

* Navigate file structures in the LINUX environment.

* US Citizen with ability to obtain and maintain a TS/SCI with polygraph security clearance.

Preferred Qualifications:

Understanding of the Semiconductor fabrication process and process development.

* Understanding of Process Design Kit (PDK) Development (tech files, verification rule files, Pcells, skill programing)

* Skilled in the use of the Cadence Virtuoso capture tool.

* Proficient in the use of Cadence ASSURA or Siemens Mentor Calibre DRC/LVS verification tools.

* Experience in Superconducting Reciprocal Quantum Logic circuit design practices

* Current Secret/TS SCI clearance

#NGMCENG
Salary Range: $102,400 - $160,900
Salary Range 2: $127,000 - $199,600
The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.
Employees may be eligible for a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.
The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.