Reality Labs (RL) focuses on delivering Meta's vision through AI-first devices that leverage Mixed Reality (MR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Mixed and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & MR devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. In this position you will lead a team of performance architects analyzing and optimizing the behavior of heterogeneous subsystems cooperating to enable compelling user experience via our SoCs. You will collaborate with a world-class group of system, SW, SoC and IP architects, modeling, development, and validation teams, and program/project managers to accelerate the development and market introduction of low power highly customized SoCs.

• Manage a team of performance architects to achieve program goals while increasing team skill
• Support the team to cover the complete performance life cycle, including initial modeling, architectural optimization, performance verification, post-silicon validation, and software tuning
• Collaborate across disciplines to bridge gaps, identify opportunities to accelerate/automate workstreams while optimizing SoC performance for our defined and emerging use cases
• Facilitate creation and productization of more abstract system performance models

• 7+ years of experience as a Performance Architect, Silicon Architect, Subsystem Designer, Validation Engineer for production silicon shipped in volume.
• 2+ years of Management experience
• Experience with at least two methods for analyzing performance of digital chips or systems, including at least one based on simulation of models above the RTL abstraction level
• Results oriented, self-motivated, proactive with demonstrated creative & critical thinking
• BS EE/CS or equivalent areas

• Experience in performance analysis of mobile or consumer electronics SoCs integrating heterogeneous subsystems
• Experience in SystemC or equivalent forms of Transaction Level Modeling, preferably at different levels of timing accuracy
• Experience optimizing Network on Chip or other on-chip fabrics to optimize memory system performance
• Experience bridging virtual platforms, task graph performance models, and/or emulators to timed simulation models
• Experience optimizing performance in battery-operated systems with dynamic power state changes
• Experience in computer vision, machine learning, graphics, audio, and/or display technologies