RL Silicon Power Group is looking for a Silicon Power Architect who will work with a world-class group of researchers and engineers. This ideal candidate will understand the full spectrum of silicon power modeling, analysis, optimization and projections from algorithms on generic compute units to custom silicon IP blocks, traditional compute benchmarking, and SOC and System level implications. The candidate will work with architecture, design, backend, system and verification teams and drive the team towards implementing the most power efficient design for AR/VR optimized silicon.

Silicon Power Architect Responsibilities:

• Model and own use-case power for custom silicon by working closely with systems team.
• Influence the overall SOC IPs Power requirements including power states, high level power tree & power sequence requirements.
• Work closely with Architects of SOCs that optimizes functions such as image compute and CPU/GPU workloads for our AR/VR products.
• Work closely with PMIC & systems teams on the overall SOC Power Requirements.
• Optimize the power architecture implementation to meet use case power goals.
• Work across disciplines, brainstorm big ideas, build new methodologies, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product.
• Understand the tradeoffs between general purpose and custom compute mechanisms, be able to model data-flows, and create detailed cost/benefit analysis.
• Work on post silicon model to hardware correlation.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 3+ years of experience with production silicon including at least one product shipped.
• Experience with methods for partitioning a solution across hardware and software, digital, and other multi-disciplinary boundaries in a system solution.
• Experience evaluating architectural trade-offs of performance, power, and area.
• Experience employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary system issues.
• Knowledge of low power design principles across RTL, design and system level.

• MSEE or PhD equivalent.
• Experience in top down high-level-model to HW power modeling of system use cases. Familiarity with high-level modeling tools like Synopsys Platform Architect or virtual prototyping tools is a plus.
• Experience in technology node scaling and projections.
• Experience in custom IP block power estimates.
• Experience programming in C, C++ or Python.
• Experience working effectively as an individual and in a multidisciplinary team.
• Skills of dealing with ambiguity with a fast changing consumer electronics field.
• Results oriented, self-motivated, proactive with demonstrated creative & critical thinking.
• Experience to collaborate and/or lead in a team environment.