Silicon Physical Design Engineer

Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. In this position, you will work with Machine Learning (ML) front-end and back-end hardware designers to drive the Physical design implementation of ML compute blocks in advanced technology nodes and develop custom methodologies to optimize the PPA (Power, Performance, and area) of the design.

• Develop and own physical design implementation of multi-hierarchy low-power ML Hardware design including physical-aware logic synthesis, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Collaborate with ML architects and designers to understand the ML workloads and develop custom physical design methodologies and recipes to optimize the PPA of ML compute datapath design blocks.
• Work across disciplines, brainstorm big ideas, work in new technology areas, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product
• Travel both domestically and internationally

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 10+ years of experience in ASIC Physical Design
• Understanding of RTL2GDSII flow and design tapeouts in 3nm or below process technologies.
• Experience with low power implementation, power gating, multiple voltage rails, UPF knowledge.
• Experience working with EDA tools like Fusion Compiler, ICC2/Innovus, Primetime, RedHawk
• Experience with Python, TCL, Perl programming.
• Demonstrated experience of proactively identifying, scoping and implementing new solutions.

• Experience running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
• Experience in Block-level and Full-chip floor-planning and power grid planning.
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques
• Experience in hardware microarchitecture or RTL design
• Master/PhD degree in EE/CS or equivalent areas