Reality Labs (RL) focuses on delivering Meta's vision through AI-first devices that leverage Mixed Reality (MR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Mixed and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & MR devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.As part of the Reality Labs SoC Performance team, the candidate will help lead performance modeling, correlation, workload profiling, and analysis efforts. The ideal candidate for this role will have an excellent grasp on SoC architecture/micro-architecture, experience in developing performance models and collecting performance analysis data to guide the architecture of next generation SoCs. Successful candidates are motivated self-starters who are comfortable operating in a cross-functional environment, and have a hands-on approach to problem-solving.

• Performance evaluation and bottleneck analysis of existing and future SoCs
• Performance modeling of IP components and modeling of SoC fabric and DRAM
• Profile and extract system-usage behavior of workloads and design micro-benchmarks
• Create analytical models to project performance between (n-1) to next-gen product
• Identify and evaluate firmware/software optimization opportunities and solidify HW-SW co-design
• Work across disciplines, collaborate with vendors, brainstorm big ideas, build new methodologies, juggle/coordinate multiple initiatives

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• MSEE/CS or equivalent experience
• Understanding of SoC Architecture, NoCs, memory sub-system, Quality of Service (QoS), and heterogeneous compute principles.
• Experience with SoC/IP/System performance modeling and correlation
• Understanding of basic power concepts and trade-offs
• Experience in data analysis and problem-solving, including designing performance experiments, collecting and analyzing data, and drawing conclusions.
• Experience with programming (C/C++/SystemC or Python), scripting, automation and data visualization

• Experience working with cycle-accurate performance models and frameworks for performance architecture evaluations for various SoC architecture components (Accelerators, NoC, DRAM, MMU, etc)
• Proven experience working collaboratively in a team environment, with strong communication skills
• Experience with bare-metal programming, micro-benchmarking, performance instrumentation, Simpoints, etc.
• Experience with RTL design verification