As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design, physical design, and verification skills to integrate state of the art machine learning accelerators into custom SOCs, and contribute to power and performance optimization through power aware simulations, gate level simulations and performance simulations. You will work closely with SOC vendors, Validation teams, ML researchers, architects and designers in creating functional and physical integration requirements and test cases for multiple state of the art SOCs.

Design Verification Engineer Responsibilities:

• Work with researchers and architects defining power and performance targets, and supporting power states and verification methodologies for the ML accelerator.
• Define and track detailed internal integration test plans for top-level design components, and SOC vendor test plans and use case testing.
• Drive gate-level simulation health for internal netlists and SOC vendor netlists.
• Implement scalable power aware simulation and gate level simulation infrastructure leveraging test benches in System Verilog.
• Keep track of power state coverage metrics and bugs encountered and fixed.
• Support post silicon bringup and debug activities.
• Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 10+ years of experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
• Experience in EDA tools and Python scripting used to build tools and flows for verification environments.
• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
• Track record of 'first-pass success' in ASIC development cycles.

• Masters in Electrical Engineering or Computer Science.
• Experience in development of UVM based verification environments from scratch.
• Experience with low power design.
• Experience working with vendor, SOC teams and Validation teams.
• Experience mentoring other design verification engineers.