Meta is looking for an experienced ASIC Packaging Engineer, Mechanical/Thermal modeling focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

ASIC Packaging Engineer Responsibilities:

• As an ASIC Packaging Engineer, you will work with cross functional teams to define advanced package thermal/ mechanical specification for advanced packages 2.5d, 3D, wafer level packaging.
• Perform advanced package modeling for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging to ensure our ASICs meet/exceed performance and reliability targets
• Model and simulate package manufacturing and assembly process for advance packaging process chip on wafer on substrate (S/L/R), silicon interposer, HBM attach, package to board SMT process
• You will work with cross-functional teams from ASIC R&D and manufacturing to drive the mechanical/thermal design using advanced FEA of new ASICs, and make engineering trade offs with package warpage, stress, reliability, thermal performance
• Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors
• Perform advanced package stress analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package manufacturability and reliability for next generation versions of current products
• Packaging materials (e.g. underfill, mold compound, solder ball metallurgy, TIM, substrate, and lid attach adhesive) characterization to support new packaging architecture and develop material models to precisely describe package physical behavior
• Responsible for designing robust and reliable mechanical package architecture

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 10+ years of experience in FEA modeling or PhD in Mechanical Engineering or similar field and 7+ years of experience in FEA modeling
• Experience with complicated numerical simulation results against first principles such as strength of materials solutions
• Consider as an expert with hands-on experience of major FEM tools with skill to calibrate modeling and results with existing empirical data
• Hands of mechanical modeling stress analysis experience for interposer or fanout package design for both organic and inorganic interposer with or without bridges such as Cowos-L, cowos-R, EMIB, 3D IC structural concept and for lided or lidless package
• Proven fundamentals in the electrical/material/thermal or mechanical engineering field(s).
• Proven communication skills and experience working effectively with cross-functional teams

• Master's or PhD degree in Materials engineering
• Experience and prior experience of taking products from concept to prototyping and production
• In-depth knowledge of modeling of flip chip, 2.5D and 3D and wafer packaging technologies package design
• Hands-on experience using FEM tools(e.g., ANSYS, ABAQUS, COMSOL etc.) in the creation of complex models,
• Programming experience using Matlab, Python and fundamental machine learning capability is plus