ASIC Package Engineer SI/PI

Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

ASIC Package Engineer SI/PI Responsibilities:

• Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization to involved in the product definition and optimize chip floorplan, power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology
• Drive package level Lead ASIC package SI/PI design activities, including substrate stackup/material selection, design guide implementation, layout review, and post-layout analysis
• Lead pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI design
• Lead SIPI validation methodology and develop detailed engineering test plans
• Conduct post Si validation and qualification of high speed interface for ASICs
• Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow
• Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis
• Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies.
• Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 10+ years of experience with signal integrity analysis, simulation, and measurement
• Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
• Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)
• Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc).
• Familiarity with post Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed serdes.
• Familiarity to next generation memory and chiplet standards and timing budget methodology.
• Package-level signal integrity and power integrity understanding including silicon, package, and board.

• Master degree or PhD in Electrical Engineering, Physics, Mathematics, or related field (or equivalent experience)
• 7+ years of experience in SIPI simulation and validation areas
• Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBM and USB.
• Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
• Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc.
• 5+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process
• Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams.
• Solid understanding and experience in computational electromagnetics and transmission line theory.