ASIC Engineer, Physical Design

Meta is seeking an ASIC Engineer to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design implementation of advanced IPs using state-of-the-art tools. Come work and learn alongside our ASIC engineers to build "Green" data center accelerators.

ASIC Engineer, Physical Design Responsibilities:

• Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs.
• Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.
• Drive logic/physical synthesis and generate optimized Gate level Netlist for Physical Design.

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• Programming/scripting skills: TCL, Python, or Shell
• Knowledge of geometry/process/device technology implications on physical design
• Knowledge of Computer Architecture, Digital Design or VLSI Design
• Knowledge of RTL2GDSII flow
• Knowledge of CMOS Technology, Logic Gates, Flip Flops or similar
• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment

• Knowledge of Verilog, VHDL or similar hardware description language
• Experience with Logic Synthesis
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
• Understanding of SRAM Memories