Meta is hiring ASIC Methodology Engineers within our Infrastructure organization to work on design integrity and signoff methodology development. We are looking for individuals with experience in timing signoff flow/methodology development for large complex disaggregated ASICs, with exposure to library characterization, STA, modeling, extraction, variation analysis, aging, and signoff flows to build efficient System on Chip (SoC) and IP for data center applications.
ASIC Engineer, Methodology Responsibilities:
- Work with our ASIC vendor partners and Foundries to assess signoff margins and tradeoffs at design/arch/process-tech levels and drive PPA and design integrity for Meta SOCs.
- Develop Meta's internal timing signoff methods and flows, establishing signoff policy, timing corners, extraction, aging, and reliability metrics, for IP and SOC, from synthesis to Tape Out.
- Define and develop checklists and audits for IP and SOC development milestones including TO, from a timing signoff perspective.
- Develop robust timing signoff automation and test structures to ensure Meta's timing methodology is A0-production ready.
- Drive test-chip/IP methodologies as necessary to update Meta's signoff requirements for new process technologies.
- Partner with EDA tool vendors to select and deploy the appropriate timing signoff features and flows to improve productivity and ensure design integrity.
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- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 12+ years of experience with STA, modeling, signoff methodology development, variation analysis, etc.
- Experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments.
- Experience with library characterization, process technology evaluation, and test chip development for better understanding of process technology across multiple nodes/foundries.
- Experience with aging and reliability methodologies, and associated flow development.
- Experience with IP modeling and integration into SOC from a timing/signoff perspective.
- Experience with Post-silicon bring-up, debug and identify any process/timing related issues.
- Experience managing multiple design releases and working with cross functional teams to support and debug timing signoff issues.
- Experience with communicating across functional internal teams and with vendors Knowledge of front-end and back-end ASIC tools.
- Experience with RTL design using SystemVerilog or other HDL.
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Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.
$212,000/year to $291,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.