Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class Inference and Training performance. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.

ASIC Engineer, Design Responsibilities:

• Micro-architecture development.
• RTL development using Verilog, System Verilog and HLS.
• Lint, CDC, Synthesis, & Power Optimization.
• Soft and hard IP identification, selection and integration.
• Collaboration with verification and emulation teams in test plan development and debug.
• Collaboration with implementation team to close the design on timing and power.

• 3+ years of silicon development experience.
• Experience with Verilog or System Verilog.
• Experience in one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs, or Experience in SoC Micro-architecture, Design and Integration, or Implementation, Power methodology development.
• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

• Experience in data path development.
• Experience with Synthesis and Timing Closure.