Infosys is seeking ASIC Lead and is a global leader in technology services and consulting. We enable clients in more than 50 countries to create and execute strategies for their digital transformation. From engineering to application development, knowledge management and business process management, we help our clients find the right problems to solve, and to solve these effectively. Our team of 190,000+ innovators, across the globe, is differentiated by the imagination, knowledge, and experience, across industries and technologies that we bring to every project we undertake.
Required Skills
Candidate must be located within commuting distance of Markham or Longmont Ontario or be willing to relocate to the area. This position may require travel.
Want more jobs like this?
Get Software Engineering jobs in Markham, Canada delivered to your inbox every week.
Bachelor's degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
At least 4 years of Information Technology experience.
Candidates authorized to work for any employer in Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time.
KEY RESPONSIBILITIES:
- Developing block and SoC timing constraints, f ull chip STA setup and signoff of multi-corner multi-voltage designs.
- Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
- Engaging closely with block and SoC d esign teams to understand the design requirements , STA constraints, and convergence challenges.
- Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures
- 10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs.
- Demonstrated ability in areas of ASIC STA constraints generation, timing analysis , timing convergence, and ECOs , at both block and full chip level, is a must
- Implementation experience and knowledge handling multi-voltage design i s expected. STA closure of l ow power and multi-power mode designs is an added advantage.
- Expertise in industry standard ASIC EDA tools , including Synopsys DC and Primetime is required.
- Proficiency in scripting language, such as, T C L, Perl and/or Python
- Experience developing scripts to automate design flow, analysis
- Hands-on experience with Physical Design implementation is a plus
- Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
- Strong analytical/problem solving skills and pronounced attention to details.
Estimated annual compensation range for the candidate based in the below location will be:
Ontario: $ 89004 to $115491