Introduction
The High Speed IO design team delivers both proprietary and industry standard interfaces for IBM's POWER systems' and Z Mainframe's processors. With a current data rate up to 64Gbps and rising, verifying the functionality of the digital and analog components in an efficient manner is necessary.
Your role and responsibilities
Job Duties:
A verification engineer should be able to create test plans and testbenches to verify both logic and microcode provided by logic designers. They should communicate with the logic designer to create and review a test plan document, and then implement a testcase from the document. Testcases are written in either cycle sim or event sim, depending on the application. Simulations should be randomized appropriately and executed in large numbers through batch submissions. Coverage should be collected and analyzed with the logic designer. Some amount of logic debug ability is expected.
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About the Team:
The team in Austin, TX consists of analog circuit designers, logic designers, and verification engineers. We work with a global team to deliver IBM's proprietary high speed interfaces for its server processors.
Skills:
High-speed IO or Analog Mixed Signal Verification experience preferred, Testbench design, Automated testcase design (Fusion/C++), Sim coverage collection and analysis, Batch submission and queue management, Randomization management, General communication skills (written and on the phone)
Tools:
C/C++, SystemVerilog, UVM, Git, VHDL, AMS verification, Linux OS, KornShell & BASH scripting, NCSim, MESA / Fusion, HDWB, AWAN, Mantis, PSL
Required education
Bachelor's Degree
Preferred education
Master's Degree
Required technical and professional expertise
A minimum of 7+ years of verification experience in high-speed I/O or analog mixed-signal domain.
Demonstrated experience in Verification
Proficiency in C++
Familiarity with C programming
Preferred technical and professional experience
Familiarity with IO SERDES design, Mixed Signal Analysis, and design verification
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