Layout Designer - Memory

and will be involved in automation efforts on the memory team

Your role and responsibilities

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. The designer should be able to automate

Required education

Bachelor's Degree

Preferred education

Master's Degree

Required technical and professional expertise

6-8 Years of relevant experience in SRAM layouts or standard cell library development for lower technology nodes like 7nm and below.

1) Experience in developing memories like Caches, CAMs, Register files, multiport register Files, Compilers etc
Or layouts for Combinational logical cells Inverter, Buffer, AND, NAND, OR, NOR, XOR, XNOR & Complex cells, latches, LCBs and
Miscellaneous cells Tie cells, Tap cells, Decaps, Filler cells.
2) Good experience in Skill or tcl/Python scripting is a must
3) Should be in a position to work hands on layouts
4. Good team worker with multi-discipline, multi-cultural and multi-site environments
5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms
6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions
7) Work closely with required global teams to ensure the success of the whole project
8. Leadership to drive collaborative initiatives with cross teams.

Preferred technical and professional experience

For standard cell design: Experience of End to end testing and library release is a plus

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