Introduction
In this role, you will join a world-class team of engineers and researchers and contribute to the development of innovative integrated circuits implemented in deep submicron CMOS (Complementary Metal-Oxide-Semiconductor) technologies. We focus on innovative circuit designs for a range of emering applications such as AI accelaration, high-speed communications, and chiplet-based integration approaches, among others.

Your Role and Responsibilities

This is for a 2025 summer internship with the following start dates: May - August or June - September for quarter system schools.

• Collaborate on architecture/system-level development. This will involve the analysis of trade-offs using system simulations and/or software and may also involve the analysis of measured data from existing/prior ICs.
• Perform design and/or synthesis of digital and/or mixed-signal circuit building blocks to meet a set of specfications.
• Perform co-simulation and verification of the designed circuits and sub-systems.
• Support physical design/synthesis and post-layout verification.
• Document design concept, simulation, and verification results.

• Applicants should be PhD & MS students pursuing graduate studies.
• Have experience with relevant industry-standard IC-development tools such as Cadence.
• Have experience with design using deep sub-micron CMOS technologies.
• Possess a track record of success in completing complex mixed-signal and/or digital IC designs.
• Successfully create and communicate technical ideas.

• Knowledge of AI-accelertor architectures.
• Knowledge of chiplet-based system implementation approaches and their assosciated communication interfaces.
• Applied knowledge of standard-cell digital design, custom digital design, and/or mixed-signal design for high-speed communications.
• Knowledge of common programming languages such as Python.