Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience with RTL coding using Verilog/SystemVerilog.
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 8 years of experience in ASIC design with 3 years of experience working on PCIe design.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience with scripting languages (e.g., Tcl, Python or Perl).
- Experience developing common library RTL modules and working on PCIe verification and bringup.
- Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a TPU SoC RTL Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on PCIe subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Work mostly independently to create and review PCIe subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.