Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related field, or equivalent practical experience.
- 8 years of experience with analog and mixed signal IP.
- Experience in architecting System-on-a-Chip (SoC) clocking or designing Phase-locked Loop (PLL) or Analog-to-Digital Converter (ADC).
- Experience in working with or managing silicon IP vendors
- Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, a related field, or equivalent practical experience.
- Experience in co-architecting an SoC with AMS IP such as PLL to optimize Power, Performance and Area (PPA).
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will manage IP vendors, negotiate technical features, schedule through Statement of Work (SOW) and unveiling performance, area and power optimization and design risks. You will be responsible for SOW closure, ensuring the specifications and the milestones fit the product priorities and schedule. You will work with In-Process Quality Assurance (IPQA) team to provide specifications to build flows for proper quality checks and IP intake.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Map the IP ecosystem, plan and anticipate future Account Management Service (AMS) IP product requirements.
- Work with Architecture, Product Management, Design and SoC IP Integration and IP Quality Assurance (QA) leads.
- Work closely with IP vendors to identify new features, negotiate schedule, influence vendor IP portfolio to maximize Google product differentiation.
- Drive Statement of Work (SOW) and Engineering Change Orders (ECOs), change and version controls and develop IP QA checklists and guidelines.
- Ensure that the IPs are meeting our Design for Excellence (DFX), Domain Validation (DV), software, testing and characterization requirements by defining and specifying deliverable requirements for analog IP.