Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 6 years of experience working in a signal integrity technical environment, or 5 years of experience with an advanced degree.
- 3 years of experience in technical leadership.
- PhD in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- Experience with Allegro, HFSS, SIwave, ADS, Matlab, PowerDC, PowerSI.
- Experience with the product development process for mass volume production design, with a focus on signal integrity, power integrity and lab validation.
- Lab experience with SerDes testing. Understanding of SERDES capabilities.
- Scripting experience for data collection and analysis (e.g., Python, bash). Understanding of FEC and its implications for system design.
- Familiarity with PCIE, DDR, SATA, Ethernet standards, PCB, connector, and/or cable design and assembly processes, including materials and component selection.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by custom hardware designed and made in-house.
As a Staff Signal Integrity Engineer, you will design and build the systems that are the heart of our largest and powerful computing infrastructure. You will see those systems from concepts all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users.
The US base salary range for this full-time position is $168,000-$252,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Lead System SI design on data center hardware products.
- Collaborate with board, chip and system engineers, design partners, and chip vendors, to drive system SI design, explore layout and manufacturability tradeoffs, and ensure that product functions as required.
- Drive ASIC, package, board, connector, and cable vendors to develop new interconnect technologies.
- Participate in system interconnect bring up and qualification, working with test engineers and including configuring chips to ensure adequate margin.
- Drive solutions for SI issues with design engineers, PCB designers, and system team. Run trade-off analysis on performance and cost.