Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
- Experience with C++.
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.
- Experience with hardware modeling, design, verification, or architecture.
- Experience with hardware or software architecture.
- Experience with Python.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Implementing a design in a C-model lets you understand the design at a much deeper level than would be possible if you were only reading specs. This makes it possible to identify potential problems earlier in the design process and makes you a valuable bridge between architecture and design.
We develop C++ models of the on chip interconnect, parts of the memory subsystem and other parts of the chip. The models implement the design of the real hardware at a low level to allow us to very accurately model the performance of the design. We correlate these results with RTL simulations and silicon to confirm that the model is accurate. We work closely with the architecture team to understand use cases and requirements and to suggest improvements, with the design and DV teams to correlate the results and understand performance implications of physical design and power related features.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities
- Explore and evaluate the architectural design choices for network-on-chip, system coherency, and memory system.
- Develop C-models, simulate and analyze performance and power trade-offs.
- Work with hardware design and verification teams to correlate the simulated performance of the C-models with the Register-Transfer Level (RTL) design and silicon.
- Work with other hardware and software architects to understand and improve the architecture.