Minimum qualifications:

• Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
  
• 5 years of experience in developing test and debug infrastructure.
  
• Experience with programming languages such as C/C++ or Python.
  

Preferred qualifications:

• Master's degree in Computer Science or Electrical Engineering.
  
• Experience with DDRPHY and DRAM tuning and characterization, and PVT.
  
• Familiarity with using Prototyping platforms like Emulators or FPGAs.
  
• Familiarity with power and performance measurement of SoCs.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Work with Architecture, Design, and Product teams to understand requirements for memory subsystem validation (DDRPHY, Memory Controller, DRAM).
• Understand the design and develop/execute validation tests to establish functionality of new design on emulation platform for tapeout for DDRPHY and DRAM subsystem.
• Drive the post silicon bringup and validation activities for the DDRPHY/DRAM interface, including its tuning and characterization.
• Develop various post silicon validation/debug/margin tools related to DDRPHY and DRAM.
• Debug failures with cross-functional teams for Emulation, Silicon, Boards, Software, Manufacturing.