Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 1 year of experience in RTL coding using Verilog or Systemverilog language.
- Experience in one or more SoC Integration domains and flows (e.g., clocking or debug or fabrics/Network on Chip (NoC) or security or low power methodologies).
- Experience with programming languages (e.g., Python, C/C++ or Perl).
- Domain knowledge in one or more of these areas: process cores, interconnects, debug and trace, security, interrupts, clocks/reset, power/voltage domains, pin-muxing.
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About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be part of a team developing System-on-a Chip (SoC) used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area. You will collaborate with other design team members to specify and deliver high quality designs for next generation data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Participate in design, implementation and Integration of SoC chassis and subsystems.
- Perform Register-Transfer Level (RTL) coding for subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
- Perform quality check flows (e.g., Lint, CDC, RDC, VCLP.)
- Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.