Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 7 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
  
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master's degree in Electrical Engineering.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.
  
• Experience with layout verification and design rules.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing cutting-edge SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Define and drive the implementation of physical design methodologies.
• Take ownership of one or more physical design partitions or top level.
• Manage timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.