Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques.
- Experience with a scripting language such as Perl or Python.
- Master's degree or PhD in Electrical Engineering or Computer Science.
- Domain knowledge in one or more of the following: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, or PinMux.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems including Micro architecture, RTL coding, definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for quality and optimized security designs. You will be involved in Micro-Arch and RTL coding for imaging and video codecs - IPs and subsystems. You will also contribute to improvements by debugging and using different RTL QC tools like Lint, CDC, or VCLP.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with ASIC RTL engineers on sub-system and chip-level integration activities including: plan tasks, hold code and design reviews, contribute on sub-system/chip-level integration.
- Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance and area for sub-system/chip-level integration.
- Interact closely with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones, and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
- Work closely with the cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and represent project status throughout the development process.