Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 1 year of experience in verification of IP designs (e.g., CPU, Peripherals, PMU, etc.).
- Experience with SystemVerilog, SVA and functional coverage.
- Experience with verification methodology (e.g., UVM, OVM, VMM).
- Master's degree in Electrical Engineering or equivalent practical experience.
- Experience creating and using verification components and environments in standard verification methodology.
- Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will collaborate with design and verification engineers in active projects and perform verification. You will also build efficient constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the life-cycle of verification, from verification planning to test execution, to collecting coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Manage coverage measures to identify verification holes and show progress towards tape-out.