Experience with SerDes testing in a lab setting, and familiarity with PCIE, DDR, SATA, and Ethernet standards.

Understanding of SERDES capabilities, and FEC and its implications for system design.

Familiarity with PCB, connector, or cable design and assembly processes, including materials and component selection.

About the job

Lead a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved worldwide. Your expertise and leadership will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Signal Integrity Manager, you will manage your project goals, contribute to product strategy, and help develop your team. Operating with scale and speed, our hardware engineers and TLMs are just getting started -- and as a manager, you will guide the way.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $214,000-$305,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Manage, lead, and grow the System Signal Integrity (SI) design team on data center hardware products and manage against the roadmap.
  
• Be responsible for planning for the budget, resources, and tools to deliver against that roadmap. Manage system interconnect bring-up and qualification, working with test engineers, including configuring chips to ensure adequate margin.
  
• Drive solutions for SI issues with design engineers, PCB designers, and system team. Run trade-off analysis on performance and cost.
  
• Collaborate with board, chip, system engineers, design partners, and chip vendors to drive system SI design. Explore layout and manufacturability trade-offs, and ensure product functions as needed.
  
• Drive ASIC, package, board, connector, and cable vendors to develop new interconnect technologies.