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Senior SoC and IP Design Engineer, Google Cloud

AT Google
Google

Senior SoC and IP Design Engineer, Google Cloud

Tel Aviv, Israel

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
  • Experience in logic design and debug with Design Verification (DV).
  • Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Preferred qualifications:
  • Experience in scripting languages like Python or Perl.

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  • Knowledge of high performance and low power design techniques.
  • Knowledge of assertion-based formal verification.
  • Knowledge of System-on-a-Chip (SoC) architecture.
  • Domain knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors.

  • About the job

    Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

    Responsibilities

    • Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
    • Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
    • Participate in synthesis, timing/power closure and ASIC silicon bring-up.
    • Participate in test plan and coverage analysis of the block and SoC level verification.
    • Communicate and work with multi-disciplined and multi-site teams.

    Client-provided location(s): Tel Aviv-Yafo, Israel
    Job ID: Google-139171223073366726
    Employment Type: Other

    Perks and Benefits

    • Health and Wellness

      • Health Insurance
      • Dental Insurance
      • Vision Insurance
      • Life Insurance
      • Short-Term Disability
      • Long-Term Disability
      • FSA
      • HSA
      • Fitness Subsidies
      • On-Site Gym
      • Mental Health Benefits
      • Health Reimbursement Account
      • HSA With Employer Contribution
    • Parental Benefits

      • Birth Parent or Maternity Leave
      • Non-Birth Parent or Paternity Leave
      • Fertility Benefits
      • Adoption Assistance Program
      • Family Support Resources
      • Adoption Leave
    • Work Flexibility

      • Hybrid Work Opportunities
    • Office Life and Perks

      • Commuter Benefits Program
      • Casual Dress
      • Pet-friendly Office
      • Snacks
      • Some Meals Provided
      • On-Site Cafeteria
    • Vacation and Time Off

      • Paid Vacation
      • Paid Holidays
      • Personal/Sick Days
      • Leave of Absence
      • Volunteer Time Off
    • Financial and Retirement

      • 401(K) With Company Matching
      • Company Equity
      • Performance Bonus
      • Financial Counseling
    • Professional Development

      • Tuition Reimbursement
      • Internship Program
      • Learning and Development Stipend
    • Diversity and Inclusion

      • Employee Resource Groups (ERG)

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