Minimum qualifications:

• Bachelor's degree or equivalent practical experience.
  
• 5 years of experience in ASIC Chip Design.
  
• 3 years of experience in Python/C++ programming.
  
• Experience with hardware electronic design automation tools.
  
• Experience in writing code and design practices.
  

Preferred qualifications:

• Experience planning and deploying new tools and flows to users.
  
• Experience in AI/ML methods for ASIC development.
  
• Knowledge of chip design processes such as verification, design, and implementation.
  
• Ability to present and explain novel methods to users.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Partner with the Google Deepmind team to incorporate AI/ML techniques in chip design methodology and integrate into development flow.
  
• Partner with Chip Project teams to influence and standardize methodology across projects and functional areas (e.g., Design, Verification, Emulation, and other front end domain).
  
• Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow.
  
• Perform or guide technical evaluations of tools and their AI capabilities and drive planning for possible deployment. Collaborate with teams across Google to identify and create strategic opportunities for improved chip design across Google.
  
• Guide the development of internal software tools and automation efforts. Participate in design reviews and engage in technical and schedule trade-off discussion.