Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in Application-Specific Integrated Circuit (ASIC) performance power management or low power design/methodology.
- Experience in architecture, micro-architecture or design in Fabrics, Quality of Service (QoS), Coherent fabrics, Memory Management Unit (MMUs), Caches or Memory Systems.
- Master's degree or PhD in Computer Science, Electrical Engineering or a related field.
- Experience in designing, implementing or validating in two or more of these areas: Fabrics, QoS, Coherent fabrics, Input-output Memory Management Unit (IOMMUs), Caches, Memory Systems.
- Experience with low power architecture and power optimization techniques like power domain partition, clock gating, power gating or Dynamic Voltage Frequency Scaling (DVFS).
- Experience in SoC system pre-silicon or post-silicon performance analysis and tuning.
- Experience in SoC architecture performance analysis, tools, and simulators with knowledge of languages such as SystemVerilog, Verilog.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with stakeholders (e.g., Product Manager (PM), Software (SW), Design, Verification) to defineIntellectual Property(IP), Subsystem and ASIC specifications to meet goal requirements.
- Work with teams on pre-silicon performance or power analysis, evaluating design trade-off, writing test and validation plan and resolving implementation issues.
- Work with teams on post-silicon chip bring-ups and deep-dive perf, power or functional issues.
- Perform analysis results in both qualitative and quantitative fashion.
- Participate in evaluation of future ASIC designs and general architecture.