Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience.
- 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog .
- Experience developing and maintaining verification testbenches, test cases,and test environments.
- Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience with low power, debug, Gate Level Simulation (GLS), formal verification.
- Experience in driving cross functional teams for quality tape-outs
- Experience leading design verification of IPs, successfully delivered to many SoCs.
- Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Participating with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs.
- Be the primary point of contact for functional verification of the IP for cross-functional teams.