Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 5 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
- Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog and UVM for Application-Specific Integrated Circuits (ASIC).
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience creating and using verification components and environments in a standard verification methodology such as UVM.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Work with design verification and other stakeholders to come up with detailed test plans, dependencies, and deliverables.
- Plan the verification of complex Memory Subsystem IPs atInternet Protocol(IP) and Subsystem level by understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Work closely with design, architecture, software, silicon validation, and back-end implementation stakeholders to make technical decisions.
- Create and enhance constrained random verification environments using System Verilog and Universal Verification Methodology(UVM), or formally verify designs with System Verilog Assertions (SVA)and industry leading formal tools.