Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in DFT/DFD flows and methodologies.
- Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow.
- Experience developing DFT specifications and driving DFT architecture.
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging.
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About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define Design for Excellence (DFX)specifications and develop flows and methodologies for new technology node implementation.
- Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port(TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips.
- Work with silicon engineering team to create test plans and generate test patterns.
- Participate in post-silicon activity like bring up, diagnostics and characterization.
- Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.